Figure 1. AHL1800AUT3BC front side
This AMD K7-generation part manufactured in 2001 and marked AHL1800AUT3BC is an example of an obvious fake. Socket A CPUs have small "bridges" on the top of the package substrate, which behave as switches that control information that the chip passes to the BIOS at startup. The BIOS takes these bridge settings into firmware lookup tables to interpret the correct product brand, voltage, front side bus (FSB), and multiplier to setup the CPU. Thus, altering the bridges can alter the information passed to the BIOS, and the motherboard will run the CPU according to the altered parameters, if the silicon can stabily run.
Many motherboard BIOS can adjust voltage, FSB, and multiplier to allow overclocking. So then, why make such effort to alter the bridges?
The bridges are thin conductive fuse wires on the substrate surface. In the factory, each bridge may be laser-cut or not as needed. A cut bridge does not conduct, and represents an open switch. An uncut bridge conducts, and represents a closed switch.
Figure 2. AHL1800AUT3BC bridges L1 L2 L3 L4 L9 L10
Figure 3. AHL1800AUT3BC bridges L5 L6 L7 L8 L11
The CPU under analysis consists of a Palomino core mounted in ceramic substrate number 27100. There are 11 groups of bridges numbered L1-L11, and each of these groups contains 2 to 5 individual bridges. Within each L group, the bridges are numbered starting from 0, with a small dot or arrow marking the 0th bridge in each group. Thus, bridges may be represented generally as: La [b:0] where a = the bridge group number from 1 to 11, and where b = the highest numbered bridge in the group.
The complete set of 47 bridges are represented as:
L1 [4:0] L2 [3:0] L3 [3:0] L4 [3:0] L5 [3:0] L6 [4:0] L7 [4:0] L8 [4:0] L9 [3:0] L10 [1:0] L11 [4:0]
The exact physical method to reconfigure a bridge varies according to the CPU type. The essential objective is to be able to change a closed switch to open by physically severing a bridge wire, and/or change an open switch to closed by reconnecting a laser-cut bridge wire. In early model K7 processors such as this one, the bridges are exposed on the substrate surface. To cut (open) a bridge, all that is required is a small-bladed precision utility knife. To close a cut bridge, the bridge is drawn in its original location with a conductive ink pen, or window defroster grid repair paint. This is precise work, and care must be taken not to overlap the adjacent bridges.
Figures 2 and 3 show the reconfigured bridges. It is apparent that some of the open bridges have been changed by filling the cut area with a gray conducting filler. Note that there are two kinds of cuts that create the open bridges: the factory-made cuts are narrow - for example, the L9 bridges; the changed cuts are about twice as wide - for example, the L1 bridges. Thus, it is possible to determine exactly how the bridges were changed from factory settings by careful observation.
It seems that AMD intended bridge configuration to be performed only at factory, and although they did not publish settings information, they did publish socket pinout tables, which could help map the bridge functions because bridges connect to some pins. Thus, a guess and observe process was used to determine that each bridge group L corresponds to a particular function or parameter, and the individual bridges within each group correspond to the values available for that parameter. It was then possible to map out tables that would be similar to the lookup tables used by the system BIOS to assign values to each parameter.
A cautionary note: use at your risk. Do not assume that all possible parameters have been thoroughly tested, as some values in the tables seem to be guesses (especially the higher multipliers which are practically untestable). Much of this work was determined piecemeal, and published in overclocker forums that are now difficult to find. One good source for this information was defunct website Fab51.com which went offline in 2022 (it is still searchable in archive.org). The tables included here are based on information from Fab51.com.
For the K7 Palomino core the functions of the 11 bridge groups have been determined. See Palomino Bridges Tables 1-4 and below is a quick summary.
Examination of the bridges shows that changes were made to L3, L4, L1, L11, and L5. See table 5.
No changes were made to L10, L6, L7, L8, L2, and L9.
The original processor is a Palomino core at 10x 100 MHz FSB = 1000 MHz. The OPN should be AHL1000AUT3B. The AHL prefix corresponds to Athlon SFF, which is a mobile part for use in a SFF (Small Form Factor aka thin client) device. Note that the actual voltage can be 1.60 V or 1.50 V, depending on whether the device BIOS uses the lookup table for a desktop or a mobile part.
The bridge changes increase the multiplier to 11.5x and lock it (not sure why), change the product ID to desktop Athlon XP, and increase voltage to 1.75 V standard used by Athlon XP Palomino. If the FSB is then raised to the desktop standard, the part runs at 11.5x 133 MHz = 1533 MHz. This corresponds to AMD performance rating 1800+, and should appear to the BIOS as an AMD Athlon XP 1800+.
All that remains is to turn on the engraving tool, change the first "0" in the etched part number AHL1000AUT3B into an "8", and add a "C" to the end. The result is this unique AHL1800AUT3BC.